FMLA

z1.s and z2.s multiply lane by lane, and every active product lands in z0.s.

Instruction

fmla z0.s, p0/m, z1.s, z2.s

Types: z0.s, z1.s, z2.s — 32-bit float, 4 lanes each. Drawn at SVL = 128 bits; at SVL = 512 the same instruction pairs 16 lanes.

p0/m

z1.s

z2.s

z0.s

1 2 0 3

z0.s += z1.s × z2.s

Ready. z0.s still holds the values it had before this FMLA.

Arrow keys step, space plays or pauses.

Reading the picture

Fused, lane by lane

For each lane i the instruction does z0.s[i] += z1.s[i] × z2.s[i]. Fused means the product joins the accumulator without an intermediate rounding step.
One predicate, /m

p0/m carries one bit per lane of z0.s. An inactive lane merges: z0 keeps its old value. Click a predicate bit to switch that lane off and watch it hold still.
Contrast with FMOPA

FMLA pairs lanes of two vectors — an element-wise multiply-add. FMOPA multiplies every row by every column — an outer product into ZA. Same family of idea, very different shape.

This pass uses z1.s = {2, 1, 3, 2}, z2.s = {1, 3, 2, 2}, and z0.s = {1, 2, 0, 3} to start.