05 SVE · predicate setup
WHILELT
Two scalars in, one predicate out: lane i is active exactly while x0 + i < x1.
whilelt p0.s, x0, x1Types: p0.s — one bit per 32-bit element; x0, x1 — 64-bit scalars compared as signed integers. whilelt is the signed form; whilelo is the unsigned one. Drawn at SVL = 128 bits, so 4 bits; at SVL = 512 the same comparison writes 16 bits.
x0 + i
< x1 = 5
p0.s
p0.s[i] = (x0 + i) < x1
Ready. Set x0 and x1, then play the comparison lane by lane.
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Reading the picture
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Where predicates come from
Every SVE loop starts like this: compare two scalars and get one bit per lane. The ld1w and fmla pages let you click those bits by hand — whilelt is the instruction that sets them in hardware.
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Length-agnostic
The same instruction works at any streaming vector length. Drawn here at 128 bits it produces four bits; on hardware with a 2048-bit vector it would produce sixty-four — and the loop code would not change.
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Feeding the next instruction
This p0 is the p0/z of ld1w and the p0/m of fmla: whilelt decides which lanes those instructions touch. It also writes the condition flags First (N), None (Z) and !Last (C), so a real loop can branch on b.first / b.none instead of reading p0 back. Move x1 with the stepper and watch the active window slide.
This pass uses x0 = 2 and x1 = 5.